Some aspects of modeling of dense high speed TL interconnects for printed boards

In this paper we present some results of the ongoing research aimed at studying the limitations attached to the increase in transmission line (TL) density for the high speed interconnects at the board, multi-chip module and on-chip integration levels. For any interconnect solution the important quality in the frequency band of interest is the signal to noise ratio obtainable, where noise could be due to additional amplification required, TL itself and any cross talk signal picked up by the line. First part of the paper deals with modeling the coupling between two TL sections in the attempt to formulate simple guidelines on how to chose the TL dimensions and adjacent trace separation to maintain reasonably low trace coupling. Second part of the paper deals with the influence of TL crosssectional parameter upon the high frequency losses. Area efficiency parameter is introduced to allow the measure of the tradeoff between obtaining smaller loss (with wider central strips) and smaller cross talk in order to obtain the best possible throughput per board cross section at any bit error rate.